![]() ![]() Parallel In Serial Out Shift Register Vhdl Program For Free Assignment to a variable is immediate, the new value can be evaluated in an expression immediately. You don't show the version with count as a variable and your code isn't a. ![]() It works when 'count' is defined as a signal, however, when count is defined as a variable, the output is a constant 0, regardless of whether load is '1' or not. My code is as shown: entity qn14 isPort ( clk: in STDLOGIC reset: in STDLOGIC LOAD: in STDLOGIC X: in STDLOGICVECTOR (3 downto 0) output: out STDLOGIC) end qn14 architecture qn14beh of qn14 istype states is ( IDLE, SHIFT ) signal state: states signal count: STDLOGICVECTOR(1 downto 0) beginprocess(clk, reset)variable temp: STDLOGIC variable data: STDLOGICVECTOR(3 downto 0) beginif reset = '1' thenstate if LOAD = '1' thendata:= X output if LOAD ='1' thenoutput = 3) thenstate. The input X is a 4 bit ( 3 downto 0 ) input, what I want to make the program do is constantly output 0 when the register has successfully output all the btis in the input.It works when 'count' is defined as a signal, however, when count is defined as a variable, the output is a constant 0, regardless of whether load is '1' or not. So I've been using VHDL to make a register, where it loads in the input X if LOAD is '1', and outputs the data in serial fashion, basically a parallel in serial out register. ![]()
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